1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a subfield conductive layer and method of manufacturing the subfield conductive layer between source/drain implant regions.
2. Description of the Related Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by a conductor which extends over a dielectric which separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation and interconnect routing technologies are two of many critical aspects involved in fabricating a functional integrated circuit.
A popular isolation technology used in metal oxide semiconductor ("MOS") fabrication involves the process of local oxidation of silicon, or "LOCOS". LOCOS process involves oxidizing field regions between devices. The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, i.e., before source and drain implants are placed in device active areas. By growing a thick field oxide in field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant oftentimes redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the "shallow trench process". Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology remains inadequate for deep submicron MOS technologies. The shallow trench process is better suited for isolating densely spaced active areas having field regions less than, for example, one micron in lateral dimension.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled with a deposited dielectric. After the trench is filled, it is then planarized to complete the isolation structure.
The trench process eliminates bird's-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width.
While the trench isolation process has many advantages, there remain many problems associated with the formation of the trench and, specifically, filling of the trench. Conventional chemical vapor deposition (CVD) processes exhibit a tendency to form cusps and/or voids at the midline between closely spaced active areas hereinafter termed "silicon mesas". Those voids can lead to reliability problems and inadequate isolation performance. The planarization technique used to subsequently remove the fill dielectric from the upper surface of silicon mesas may, unfortunately, overetch the fill dielectric in the isolation areas relative to the silicon mesas. Any exposure at the silicon mesa corner or sidewalk causes inappropriate fringing field effects and/or parasitic sidewalk conduction.
Accordingly, most conventional integrated circuits employ either LOCOS or shallow trench isolation, depending upon the layout density requirements of the circuit. In addition, many integrated circuits purposefully circumvent isolation between specific devices by routing an interconnect line between devices over the grown or deposited field oxide. The interconnect generally contacts a source (or drain) region on one device to the source (or drain) region on another device. The interconnect, generally made of a conductive material such as a refractory metal and/or polysilicon serves as a conductor residing within the topography of the integrated circuit.
An interconnect extending along the topography of the integrated circuit, between devices, adds to the non-planarity of the overall structure. Generally speaking, a LOCOS field oxide extends a substantial amount from the substrate, over which an interconnect only adds to that amount. A cumulative effect of a thick field oxide and an overlying interconnect worsens the non-planarity of the resulting semiconductor topological surface. An overlying interlevel dielectric must be considerably planarized in order to achieve accurate patterning of subsequent levels of interconnect. It would therefore be desirable to produce a conductive layer which does not reside in the semiconductor topography. That is, the desired conductor must be one which is not formed on top of the field oxide. Accordingly, the desired conductor must not add to the non-planarity of the overall circuit. Further, the desired conductor must be formed entirely within the normal fabrication flow necessary to manufacture an MOS circuit.